Chiplet Effort Plays First Proposals

Open source initiative outlines interfaces and issues

EE TIME – By Rick Merritt, 03.29.19

SAN JOSE, Calif. – A group claiming members from 53 companies held its first workshop on creating an open standard for chiplets for accelerators. They aim to enable a low-cost alternative to SoCs at a time when the pace of advancing semiconductors is slowing.

The Open Domain-Specific Architecture (ODSA) group is working under the umbrella of the Open Compute Project, founded by Facebook, that recently announced its first open-source silicon project. It faces steep technical and business hurdles getting market traction, and it’s not yet clear whether it will get the broad participation its ambitions require.

To date, individual companies have made early efforts in creating their own chiplet ecosystems including Marvell’s MoChi, Intel’s EMIB and an offering from startup zGlue. Last summer, Intel released as open source the AIB protocol for its EMIB package as part of its work in a DARPA research program on chiplets.

Chiplets represent one of several efforts to compensate for slowing gains in silicon process technology. They have their roots in multi-chip modules, born in the 1970s, and more recently revived as a cost-saving technique in products such as AMD’s Ryzen and Epyc x86 processors.

“Today all multichip interfaces are proprietary. What we want as a group is to make an open interface, so you can assemble a best-of-breed chip,” said Bapi Vinnakota, an engineer at Netronome, an ODSA founder that aims to offer to the group the RTL for the 800 Gbits/second fabric used in its multicore network processors.

As a start, other ODSA members proposed at the workshop a simple “bunch of wires” as an initial physical-layer interface. It could be run on organic substrates at selectable rates of 1, 2, or 4 Gbits/second/pin.

Future interfaces could include CCIX, 112G and 56G serdes and the RISC-V TileLink. The group proposed using the PCIe PIPE abstraction layer to enable a variety of protocols and PHYs in the future. While its membership is mainly focused on the data center, ODSA ultimately aims to enable chips for mobile and edge systems, too.

The group will support a mix of coherent and non-coherent memory links and could enable bi-directional traffic as a turbo mode. It appears to have rejected Intel’s AIB protocol as too limited in data rates and pinouts.

ODSA plans to create a proof-of-concept based on PCIe before the end of the year. In tandem it will flesh out its PHY, protocol and other specs, suggesting engineers could start work on commercial implementations next year.

The group also aims to define a business flow for chiplets. It will articulate value propositions for different industry segments and define a test certification for known good die, said Sam Fuller, a marketing director at NXP, another ODSA founder. ODSA also needs to attract several key players including packaging vendors, he added.

Other active members include FPGA vendor Achronix that is overseeing the proof-of-concept and On Semiconductor which is providing perspective on power and thermal issues. Startups Kandou, SiFive and zGlue are also co-founders.

About 70 people attended the inaugural event, including about 20 on a livestream. “Every two or three weeks we get four or five new smart people involved,” said Vinnakota of the group that started in October with seven companies.

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